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Rev 1; 5/06
Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator
General Description
The MAXQ3210 microcontroller is a low-power, 16-bit RISC device that incorporates a driver for a high-output piezoelectric horn/transducer, an analog comparator, and a high-current I/O pin that directly drives an LED. The device is uniquely suited for cost-conscious applications such as chemical detectors, alarm systems, and white goods, but can be used in any application that requires high-performance and low-power operation. The high-performance 16-bit RISC core and 8-bit accumulators are complemented by standard amenities such as timers and digital I/O. The power consumption per MIPS ratio is among the best in the 16-bit microcontroller industry. The MAXQ3210 is powered directly from a 6V to 9.5V source, such as a battery, but an internal voltage regulator operates the core at 5V. The microcontroller also provides a flag if the input voltage supply falls below the low-batttery detection threshold (VBF), which can be used to signal a low-voltage condition of the 9V battery. The MAXQ3212 is a general-purpose version of the MAXQ3210 that is powered directly from an external 5.0V supply. A 1kWord EEPROM program memory stores customer application code and software algorithms. Software is programmable in-system by the ROM-based bootloader and also in-application programmable under user software control. The device provides 64 bytes of volatile SRAM and 128 bytes of EEPROM in the data memory space. Contact Dallas Semiconductor concerning the availability of ROM-based devices for highvolume, low-cost applications.
Features
High-Performance, Low-Power, 16-Bit RISC Core DC to 3.58MHz Operation, Approaching 1MIPS per MHz Low-Cost Operation from "Colorburst" Crystal or RC Oscillator 6V to 9.5V External Voltage Supply Operates from Single 9V Battery 5.0V Nominal Internal Operation Up to 15 General-Purpose I/O Pins 33 Instructions, Most Single-Cycle Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement Two Loop Counters 4-Level Hardware Stack 16-Bit Instruction Word, 16-Bit Data Bus 16 x 8-Bit Accumulators JTAG Debug/Visibility Port Program and Data Memory 1kWord EEPROM Program Memory, Mask ROM for High-Volume Applications 128 Bytes EEPROM Data Memory 60,000 EEPROM Write/Erase Cycles 64 Bytes SRAM Data Memory In-System Programming Peripheral Features Piezoelectric Horn Driver 16-Bit Programmable Timer/Counter with Prescaler High-Current I/O Pin Suitable for LED Drive Programmable Watchdog Timer Selectable Power-Fail Reset Power-On Reset (POR) Wake-Up Timer Internal 8kHz Ring Oscillator Flexible Programming Interface Integrated Bootloader In-System/In-Application Programming of EEPROM Through JTAG Ultra-Low-Power Consumption < 6mA at 3.58MHz 5.5A Standby Current (typ) Low-Power Divide-by-256 Mode Analog Features Analog Comparator Uses Internal or External Voltage Reference +2.5V Reference Output Available On-Chip Voltage Regulator Supports Up to 9.5V as Power Supply Low-Battery Detection 5V Regulated Output Available, Up to 50mA
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MAXQ3210
Applications
Gas and Chemical Sensors Security Alarm Systems Environmental Systems Battery-Powered and Portable Devices Electrochemical and Optical Sensors Home Appliances Thermostats/Humidity Sensors
Typical Operating Circuits, Pin Configuration, and Ordering Information appear at end of data sheet. MAXQ is a registered trademark of Maxim Integrated Products, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
______________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Digital I/O Pin Relative to Ground ...................................-0.5V to (VDDINT + 0.5V) Voltage Range on Any Analog I/O Pin Relative to Ground..............................-0.5V to (VDDINT + 0.5V) Voltage Range on VDD Relative to Ground .........-0.5V to +10.5V Voltage Range on FEED Relative to Ground..........-0.5V to +20V Continuous Output Current (any single I/O pin) .................25mA Continuous Output Current (all I/O pins combined) ...........25mA Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Soldering Temperature .......................................See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VDD(MIN) to VDD(MAX), CREGOUT = 10F + 0.1F, CVDD = 1F, TA = -40C to +85C. Typical values are at TA = +25C.) (Note 1)
PARAMETER Supply Voltage Internal Regulated Supply Voltage Voltage Regulator Output Low-Battery Detection Threshold Power-Fail Reset SYMBOL VDD VDDINT VREGOUT VBF VRST IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 ISTOP1 Stop-Mode Current ISTOP2 ISTOP3 RESET Pullup RRST /1 mode (Note 2) sysclk = fHFXIN /2 mode (Note 2) sysclk = fHFXIN / 2 /4 mode (Note 2) sysclk = fHFXIN / 4 /8 mode (Note 2) sysclk = fHFXIN / 8 PMM1 mode (Note 2) sysclk = fHFXIN / 256 8kHz ring mode (Note 2) Brownout detector off, wake-up timer on, TA = +50C (Note 3), VDD = 9V Brownout detector off, wake-up timer on, TA = +25C, VDD = 9V Brownout detector on, wake-up timer on, TA = +25C, VDD = 9V VRST = 0.4V, VREGOUT = 5.5V 102 Maximum ISOURCE = 50mA 0C to +85C -40C CONDITIONS MIN 6.0 4.5 4.5 7.0 6.9 4.15 6.4 4.0 2.9 2.3 1.7 0.6 7.5 5.5 51 150 TYP 9.0 5.0 5.0 MAX 9.5 5.5 5.5 7.51 7.6 4.6 9.0 6.0 4.5 3.5 3.0 1.2 33.0 13 80 250 k A UNITS V V V V V mA mA mA mA mA mA
Active Current
2
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VDD(MIN) to VDD(MAX), CREGOUT = 10F + 0.1F, CVDD = 1F, TA = -40C to +85C. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS ISOURCE = 50A max, ISINK = 50A max Turn on to 0.1% of final VREFO value (Note 3) Input Input 0.85 x VDD 0.15 x VDD FEED = 0 and 18V, VDD = 9V, typical at feed = 18V VDD = 9V, TA = +25C, ISOURCE = 16mA VDD = 9V, TA = +25C, ISINK = 16mA -50 VDD 0.5 +9 VDD 0.34 0.36 0.5 +50 0 1 MIN TYP MAX UNITS
MAXQ3210
INTERNAL VOLTAGE REFERENCE Voltage Reference Output Regulated Voltage Settling Time Input Common-Mode Voltage Input Current PIEZOELECTRIC HORN DRIVER Input High Voltage: FEED Input Low Voltage: FEED Input Leakage: FEED Output High Voltage: HORNS, HORNB Output Low Voltage: HORNS, HORNB ANALOG VOLTAGE COMPARATOR Input Offset Voltage Input Common-Mode Voltage Common-Mode Rejection Ratio VOS VCMR CMRR (Note 3) fHFIN = 3.58MHz, comparator on, comparator reference at (VDDINT - 1.5) / 2 while CMPI transitions from GND to (VDDINT - 1.5) in approximately 2ns fHFIN = 3.58MHz, V=20mV TA = +25C -50 -11 0 55 0.14 + tCLCL 0.6 + tCLCL +11 VDDINT - 1.5 mV V dB VIH2 VIL2 IIL1 VOH2 VOL2 V V A V V VREFO tREFO VREFI IREFI 2.44 2.5 1.2 VDDINT - 1.5 2.56 V ms V nA
Response Time
s
Comparator Mode Change to Output Valid DC Input-Leakage Current
0.8
1.6 +50
s nA
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VDD(MIN) to VDD(MAX), CREGOUT = 10F + 0.1F, CVDD = 1F, TA = -40C to +85C. Typical values are at TA = +25C.) (Note 1)
PARAMETER DIGITAL I/O AND OSCILLATOR Input High Voltage: Px.x and HFXIN Input Low Voltage: Px.x and HFXIN Output High Voltage: Px.x Output Low Voltage: Px.x (except P0.7) Output Low Voltage: P0.7 Input Low Current (All Ports) Input Low Current (All Ports) CLOCK SOURCES External-Clock Frequency Internal Ring Oscillator JTAG PROGRAMMING TCK Frequency fTCK JTAG programming (Note 3). Sysclk is a function of fHFXIN and the clock divisor; see IDDx parameters above JA = +85C JA = +25C 0 sysclk / 8 MHz fHFIN fRO External crystal External oscillator 1.00 0 8 3.58 3.58 MHz kHz VIH VIL VOH VOL VOL1 IL IL XTRC = 0/1 XTRC = 0/1 ISOURCE = 4mA ISINK = 4mA ISINK = 10mA Input mode with weak pullup disabled Input mode with weak pullup active, VIL = 0.4V, VDDINT = 5.5V -1 -31 0.85 x VDDINT 0.4 0.4 +1 -50 0.85 x VDDINT 0.15 x VDDINT V V V V V A A SYMBOL CONDITIONS MIN TYP MAX UNITS
MEMORY CHARACTERISTICS (Note 3) EEPROM Write/Erase Cycles EEPROM Data Retention 15,000 60,000 10 Cycles Cycles Years
Note 1: Specifications to -40C are guaranteed by design and are not production tested. Note 2: Measured on the VDD pin with VDD = 9.5V, fHFXIN = 3.58MHz, program EEPROM contains checkerboard, and not in reset. Note 3: Specification guaranteed by design but not production tested.
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
DIGITAL SUPPLY CURRENT vs. CLOCK FREQUENCY
MAXQ3210 toc01
P0/P1 HIGH OUTPUT VOLTAGE vs. SOURCE CURRENT
TA = -40C VDD = +9.0V fHFXIN = 3.58MHz TA = +25C
MAXQ3210 toc02
6 TA = -40C 5 4 IDD1 (mA)
35 30 25 IOH (mA)
3 2 1 0 0 1 2 fHFXIN (MHz)
TA = +85C
20 15 10 TA = +85C
VDD = +9.0V CLOCK SOURCE DRIVE ON HFXIN 3
5 0 0 1 2 VOH (V) 3 4 5
RC VALUE vs. OPERATING FREQUENCY
MA XQ 32 10
ANALOG COMPARATOR DELAY
MAXQ3210 toc04
toc
03
15 C (pF) 100 330 100 49.9 10 4.99 3.32
4500 4000 3500 3000 2500 2000 1500 1000 500 0
CMPI OSC2 PIN (kHz)
5V/div
CMPO
5V/div
50ns/div
R (k)
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
Pin Description
PIN 1 2 NAME GND VREF/P0.4 Ground Voltage Reference Input/Output or General-Purpose, Digital I/O, Type D Port. This pin functions as either the output of the internal voltage reference or as a bidirectional I/O. This pin can also be driven with an external voltage to provide an optional voltage reference. The pin defaults to a digital input with a weak pullup after a reset. Analog Voltage Comparator Output or General-Purpose, Digital I/O, Type D Port. This pin functions as either the output of the analog voltage comparator or as a bidirectional I/O. The pin defaults to a digital input with a weak pullup after a reset. Timer 2 Input/Output or General-Purpose, Digital I/O, Type D Port. This pin functions as either the input or output of Timer 2 or as a bidirectional I/O. The pin defaults to a digital input with a weak pullup after a reset. Secondary Timer 2 Input/Output or General-Purpose, Digital I/O, Type D Port. This pin functions as either the secondary output of Timer 2 or as a bidirectional I/O. The pin defaults to a digital input with a weak pullup after a reset. General-Purpose, Digital I/O, Type D Port. This pin functions as a bidirectional I/O, and defaults to a digital input with a weak pullup after a reset. General-Purpose, Digital I/O, Type D Port. This pin functions as a bidirectional I/O, and defaults to a digital input with a weak pullup after a reset. General-Purpose, Digital I/O, Type D Port. This pin functions as a bidirectional I/O, and defaults to a digital input with a weak pullup after a reset. Debug Port Signal TDO or General-Purpose, Digital I/O, Type D Port. This pin functions as either the TDO signal of the debug port or as a bidirectional I/O. The pin defaults to a digital input with a weak pullup after a reset. Debug Port Signal TCK or General-Purpose, Digital I/O, Type D Port. This pin functions as either the TCK signal of the debug port or as a bidirectional I/O. The pin defaults to a digital input with a weak pullup after a reset. Oscillator Input. Connect an external crystal or resonator between HFXIN and HFXOUT for system clock generation. When using a crystal, a load capacitor of approximately 22pF must be connected between this pin and ground. Alternatively, HFXIN is the input for an external clock source when HFXOUT is floating. Oscillator Output. Connect an external crystal or resonator between HFXIN and HFXOUT as the system clock. When using a crystal, a load capacitor of approximately 22pF must be connected between this pin and ground. Alternatively, float HFXOUT when an external high-frequency clock source is connected to the HFXIN pin. FUNCTION
3
CMP0/P0.3
4
T2P/P0.2
5
T2PB/P0.1
6 7 8 9 10
P0.0 P1.6 P1.5 TDO/P1.4 TCK/P1.3
11
HFXIN
12
HFXOUT
6
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator
Pin Description (continued)
PIN 13 14 15 16 17 18 NAME FEED HORNB GNDHORN HORNS VDD REGOUT FUNCTION Piezoelectric Horn Driver, Feedback. This input is connected to the feedback electrode of the horn. If FEED is not used, it should be grounded. Piezoelectric Horn Driver, Horn Brass. This output pin is connected to the piezo metal support electrode of the horn. Piezoelectric Horn Driver, Ground. This pin should be connected to GND, the same ground as pin 1. There is no special isolation required for this pin. Piezoelectric Horn Driver, Horn Silver. This output pin is connected to the ceramic electrode and provides the complementary output to HORNB when the horn output is enabled. Digital Power. This pin should be connected to a bypass capacitor to ground. Voltage Regulator Output. This pin provides the regulated output of the internal voltage regulator. This pin requires sufficient bypass capacitance, preferrably a parallel combination of 10F and 0.1F capacitors between this pin and ground. Debug Port Signal TMS or General-Purpose, Digital I/O, Type D Port. This pin functions as either the TMS signal of the debug port or as a bidirectional I/O. The pin defaults to a digital input with a weak pullup after a reset.
MAXQ3210
19
TMS/P1.2
20
Active-Low Reset Input or General-Purpose, Digital I/O, Type D Port. This pin defaults to the reset input RESET/P1.1 mode of operation following a POR. The reset input mode can be deactivated and the digital I/O mode enabled by programming the RSTD bit to 1. TDI/P1.0 Debug Port Signal TDI or General-Purpose, Digital I/O, Type D Port. This pin functions as either the TDI signal of the debug port or as a bidirectional I/O. The pin defaults to a digital input with a weak pullup after a reset. High-Current (Sink) Driver Output or General-Purpose, Digital I/O, Type D Port. This pin functions with a high-current pulldown to drive a device such as an LED or as a bidirectional I/O. The pin defaults to a digital input with a weak pullup after a reset. External Edge-Selectable Interrupt or General-Purpose, Digital I/O, Type D Port. This pin functions as either an external edge-selectable interrupt or as a bidirectional I/O. The pin defaults to a digital input with a weak pullup after a reset. Analog Voltage Comparator Input or General-Purpose, Digital I/O, Type D Port. This pin functions as either the input to the analog voltage comparator or as a bidirectional I/O. The pin defaults to a digital input with a weak pullup after a reset.
21
22
LED/P0.7
23
INT/P0.6
24
CMPI/P0.5
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
Functional Diagram
1kWORD EEPROM (PROGRAM) 128B EEPROM (DATA) PIEZOELECTRIC HORN DRIVER 64B SRAM (DATA)
COMPARATOR
16-BIT TIMER/COUNTER WITH PRESCALER
2kWORD UTILITY ROM MAXQ10 RISC CORE (16 x 8-BIT ACCUMULATORS) WATCHDOG TIMERS POWER REDUCTION/ CLOCK GENERATION POR JTAG TMS, TDI, TDO, TCK HIGH-CURRENT LED DRIVER
GPIO
EXTERNAL CRYSTAL/ EXTERNAL OSCILLATOR/ EXTERNAL RC OR RESONATOR 9V 5V VOLTAGE REGULATOR
MAXQ3210
Detailed Description
The following is an introduction to the primary features of the microcontroller. More detailed descriptions of the device features can be found in the data sheets, errata sheets, and user's guides described later in the Additional Documentation section.
Instruction Set
The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory locations. The instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. Special-function registers control the peripherals and are subdivided into register modules. The family architecture is modular, so that new devices and modules can often reuse code developed for existing products. The architecture is transport-triggered. This means that writes or reads from certain register locations can trigger other associated operations. These operations form the basis for the higher-level instructions defined by the assembler, such as ADDC, OR, JUMP, etc. The op codes are actually implemented as MOVE instructions between certain register locations, while the assembler handles the encoding, which need not be a concern to the programmer. The 16-bit instruction word is designed for efficient execution. Bit 15 indicates the format for the source field of the instruction. Bits 0 to 7 of the instruction represent the source for the transfer. Depending on the value of the format field, this can either be an immediate value or a source register. If this field represents a register, the lower four bits contain the module specifier and the upper four bits contain the register index in that module. Bits 8 to 14 represent the destination for the transfer. This value always represents a destination register, with the lower four bits containing the module specifier
MAXQ Core Architecture
The MAXQ3210 is a low-cost, high-performance, CMOS, fully static, 16-bit RISC microcontroller with EEPROM and an integrated piezoelectric horn driver and analog comparator. It is structured on a highly advanced, 8-bit accumulator-based, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle without pipelining, because the instruction contains both the op code and data. The result is a streamlined 3.58 million instructions-per-second (MIPS) microcontroller. A 4-level hardware stack, enabling fast subroutine calling and task switching, supports the highly efficient core. Data can be quickly and efficiently manipulated with three internal data pointers. Multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. The data pointers can automatically increment or decrement before or after an operation, eliminating the need for software intervention. As a result, the application speed is greatly increased.
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator
and the upper three bits containing the register subindex within that module. Any time that it is necessary to directly select one of the upper 24 index locations in a destination module, the prefix register PFX is needed to supply the extra destination bits. This prefix register write is inserted automatically by the assembler and requires only one additional execution cycle. The memory is arranged by default in a Harvard architecture, with separate address spaces for program and data memory. A special pseudo-Von Neumann memory mode allows data memory to be mapped into program space, permitting code execution from data memory. This places the utility ROM, code, and data memory into a single contiguous memory map. This is useful for applications that require dynamic program modification or unique memory configurations. In addition, another mode allows program memory to be mapped into data space, permitting code constants to be accessed as data memory. The incorporation of EEPROM for program storage allows the devices to be reprogrammed, eliminating the expense of throwing away one-time programmable devices during development and field upgrades. EEPROM can be password protected with a 16-word key, denying access to program memory by unauthorized individuals.
MAXQ3210
Memory Organization
The device incorporates several memory areas: * 2kWords of utility ROM * 1kWords of EEPROM for program storage * 128bytes of EEPROM for data storage * 64bytes of SRAM for storage of temporary variables * 4-level stack memory for storage of program return addresses and general-purpose use
PROGRAM SPACE
DATA SPACE (BYTE MODE)
DATA SPACE (WORD MODE)
64 x 16 EEPROM
A05Fh A020h A01Fh A000h
32 x 16 SRAM
87FFh 2k x 16 UTILITY ROM 8000h 4k x 8 UTILITY ROM
8FFFh 2k x 16 UTILITY ROM 8000h
87FFh
8000h
EXECUTING FROM
03FFh 1k x 16 PROGRAM MEMORY
128 x 8 EEPROM
00BFh 0040h 003Fh 0000h
64 x 16 EEPROM
005Fh 0020h 001Fh 0000h
64 x 8 SRAM 0000h
32 x 16 SRAM
Figure 1. Memory Map _____________________________________________________________________ 9
Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
Stack Memory
A 16-bit-wide internal stack provides storage for program return addresses and general-purpose use. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and interrupts serviced. The PUSH, POP, and POPI instructions can also be used explicitly to store and retrieve data to/from the stack. For the MAXQ3210, the stack is four levels deep. On reset, the stack pointer, SP, initializes to the top of the stack (03h). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the stack location pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value at the stack location pointed to by SP, and then decrement SP. password is automatically set to all zeros following a mass erase. An additional Code Lock bit set from the bootloader prevents any access to the device, even through the password. The device must be erased by the mass erase operation to clear the Code Lock bit before the device can be reprogrammed.
Programming
The microcontroller's EEPROM can be programmed by two different methods: in-system programming and inapplication programming. Both methods afford great flexibility in system design as well as reduce the lifecycle cost of the embedded system. In-system programming can be password protected to prevent unauthorized access to code memory. In-System Programming An internal bootloader allows the device to be reloaded over a simple JTAG interface. As a result, system software can be upgraded in-system, eliminating the need for a costly hardware retrofit when software updates are required. Remote software uploads are possible that enable physically inaccessible applications to be frequently updated. The interface hardware can be a JTAG connection to another microcontroller, or a connection to a PC serial port using a serial to JTAG converter such as the MAXQJTAG-001, available from Dallas Semiconductor. If in-system programmability is not required, a commercial gang programmer can be used for mass programming. Activating the JTAG interface and sending the system programming instruction invokes the bootloader. Setting the SPE bit to 1 during reset through the JTAG interface executes the bootloader-mode program that resides in the utility ROM. When programming is complete, the bootloader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software. Optionally, the bootloader can be invoked by the application code. The following bootloader functions are supported: * Load * Dump * CRC * Verify * Erase
Utility ROM
The utility ROM is a block of internal memory that starts at address 8000h. The utility ROM consists of subroutines that can be called from application software. These include: * In-system programming (bootloader) over JTAG interface * In-circuit debug routines * Test routines (internal memory tests, memory loader, etc.) * User-callable routines for in-application EEPROM programming and fast table lookup Routines within the utility ROM are user-accessible and can be called as subroutines by the application software. More information on the utility ROM contents is contained in the user's guide for this device. Some applications require protection against unauthorized viewing of program code memory. For these applications, access to in-system programming or incircuit debugging functions is prohibited until a password has been supplied. The password is defined as the 16 words of physical program memory at addresses x0010h to x001Fh. A single Password Lock (PWL) bit is implemented in the SC register. When the PWL is set to one (power-on reset default), the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to zero, these utilities are fully accessible without the password. The
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator
In-Application Programming: The in-application programming feature allows the microcontroller to modify its own program memory from its application software. This allows on-the-fly software updates in mission-critical applications that cannot afford downtime. Alternatively, it allows the application to develop custom loader software that can operate under the control of the application software. The utility ROM contains user-accessible programming functions that erase and program memory. These functions are described in detail in the user's guide for this device. memory operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major types: system registers and peripheral registers. The common register set, also known as the system registers, includes the ALU, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. The peripheral registers define additional functionality that may be included by different products based on the MAXQ architecture. This functionality is broken up into discrete modules so that only the features required for a given product need to be included. The following tables show the MAXQ3210 register set. Note that the accumulators are 8 bits wide for this device.
MAXQ3210
Register Set
Most functions of the device are controlled by sets of registers. These registers provide a working space for
Table 1. System Register Map
REGISTER INDEX 0xh 1xh 2xh 3xh 4xh 5xh 6xh 7xh 8xh 9xh Axh Bxh Cxh Dxh Exh Fxh MODULE NAME (BASE SPECIFIER) AP (8h) AP APC -- -- PSF IC IMR -- SC -- -- IIR -- -- CKCN WDCN A (9h) A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] PFX (Bh) PFX[0] PFX[1] PFX[2] PFX[3] PFX[4] PFX[5] PFX[6] PFX[7] -- -- -- -- -- -- -- -- IP (Ch) IP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SP (Dh) -- SP IV -- -- -- LC0 LC1 -- -- -- -- -- -- -- -- DPC (Eh) -- -- -- Offs DPC GR GRL BP GRS GRH GRXL BP[offs] -- -- -- -- DP (Fh) -- -- -- DP0 -- -- -- DP1 -- -- -- -- -- -- -- --
Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register is 16 bits wide. Registers in module AP are bit addressable.
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
Table 2. System Register Bit Functions
REGISTER 15 AP APC PSF IC IMR SC IIR CKCN WDCN A[n] (0..15) PFX IP SP IV LC[0] LC[1] Offs DPC GR GRL BP GRS GRH GRXL BP[offs] DP[0] DP[1] GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.0 -- -- -- -- -- -- -- -- -- GR.7 GR.7 BP (16 bits) GR.15 GR.15 GR.7 GR.14 GR.14 GR.6 GR.13 GR.12 GR.11 GR.10 GR.9 GR.13 GR.12 GR.11 GR.10 GR.9 GR.5 GR.4 GR.3 GR.2 GR.1 GR.8 GR.8 GR.0 -- GR.6 GR.6 -- GR.5 GR.5 GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9 GR.8 -- -- -- -- -- -- -- -- PFX (16 bits) IP (16 bits) -- IV (16 bits) LC[0] (16 bits) LC[1] (16 bits) Offs (8 bits) WBS2 WBS1 WBS0 SDPS1 SDPS0 GR.4 GR.4 GR.3 GR.3 GR.2 GR.2 GR.1 GR.1 GR.0 GR.0 -- -- -- -- -- SP (2 bits) 14 13 12 11 10 9 REGISTER BIT 8 7 -- CLR Z -- IMS TAP IIS XT/RC POR 6 -- IDS S -- -- -- -- RGSL EWDI 5 -- -- -- CGDS -- -- -- -- 4 -- -- GPF1 -- -- -- -- -- -- GPF0 -- -- -- -- 3 2 1 0 MOD0 E IGE IM0 -- II0 CD0 RWT AP (4 bits) MOD2 MOD1 OV -- -- ROD -- C INS IM1 PWL II1 EWT
RGMD STOP
SWB PMME CD1 WDIF WTRF
A[n] (8 bits)
BP[offs] (16 bits) DP[0] (16 bits) DP[1] (16 bits)
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator
Table 3. System Register Bit Reset Values
REGISTER AP APC PSF IC IMR SC IIR CKCN WDCN A[n] (0..15) PFX IP SP IV LC[0] LC[1] Offs DPC GR GRL BP GRS GRH GRXL BP[offs] DP0 DP1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGISTER BIT 15 14 13 12 11 10 9 8 7 0 0 1 0 0 1 0 s s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 s s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 i 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 s 0 0 s 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MAXQ3210
Note: Bits marked with an "i" have an indeterminate value upon reset. Bits marked with an "s" have special behavior upon reset. Refer to the User's Guide Supplement for this device for more details.
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
Table 4. Peripheral Register Map
REGISTER INDEX 0xh 1xh 2xh 3xh 4xh 5xh 6xh 7xh 8xh 9xh Axh Bxh Cxh Dxh Exh Fxh MODULE NAME (BASE SPECIFIER) M0 (x0h) PO0 PO1 -- -- -- -- -- EIE0 PI0 PI1 -- -- HRNC PWCN WUTC WUT M1 (x1h) CMPC -- -- -- T2CNA T2H T2RH T2CH T2CNB T2V T2R T2C -- -- -- -- M2 (x2h) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- REGISTER INDEX 10xh 11xh 12xh 13xh 14xh 15xh 16xh 17xh 18xh 19xh 1Axh 1Bxh 1Cxh 1Dxh 1Exh 1Fxh MODULE NAME (BASE SPECIFIER) M0 (x0h) PD0 PD1 -- -- KEN0 KEN1 -- -- -- -- -- ICDF -- -- -- -- M1 (x1h) T2CFG -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- M2 (x2h) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Note: Names that appear in italics indicate that all bits of a register are read-only. Names that appear in bold indicate that a register is 16 bits wide.
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator
Table 5. Peripheral Register Bit Functions
REGISTER PO0 PO1 EI0 PI0 PI1 HRNC PWCN WUTC WUT PD0 PD1 KEN0 KEN1 ICDF CMPC T2CNA T2H T2RH T2CH T2CNB T2V T2R T2C T2CFG T2V.15 T2V.14 T2V.13 T2V.12 T2V.11 T2V.10 T2V.9 T2V.8 T2R.15 T2R.14 T2R.13 T2R.12 T2R.11 T2R.10 T2R.9 T2R.8 T2C.15 T2C.14 T2C.13 T2C.12 T2C.11 T2C.10 T2C.9 T2C.8 WT19 WT18 WT17 WT16 WT15 WT14 WT13 WT12 REGISTER BIT 15 14 13 12 11 10 9 8 7 PO0.7 -- -- PI0.7 -- -- -- -- WT11 PD0.7 -- KEN0.7 -- -- CMON ET2 T2V.15 T2R.15 T2C.15 ET2L T2V.7 T2R.7 T2C.7 -- 6 PO0.6 PO1.6 -- PI0.6 PI1.6 -- -- -- WT10 PD0.6 PD1.6 KEN0.6 KEN1.6 -- ECMF T2OE0 T2V.14 T2R.14 T2C.14 T2OE1 T2V.6 T2R.6 T2C.6 DIV2 5 PO0.5 PO1.5 -- PI0.5 PI1.5 -- RSTD -- WT9 PD0.5 PD1.5 KEN0.5 KEN1.5 -- CMF T2POL0 T2V.13 T2R.13 T2C.13 T2POL1 T2V.5 T2R.5 T2C.5 DIV1 4 PO0.4 PO1.4 -- PI0.4 PI1.4 -- REFO -- WT8 PD0.4 PD1.4 KEN0.4 KEN1.4 -- CMM TR2L T2V.12 T2R.12 T2C.12 TR2L T2V.4 T2R.4 T2C.4 DIV0 3 PO0.3 PO1.3 -- PI0.3 PI1.3 -- LBF XTE WT7 PD0.3 PD1.3 KEN0.3 KEN1.3 PSS1 ECMO TR2 T2V.11 T2R.11 T2C.11 TF2 T2V.3 T2R.3 T2C.3 T2MD 2 PO0.2 PO1.2 IT0 PI0.2 PI1.2 -- LBIE WTCS WT6 PD0.2 PD1.2 KEN0.2 KEN1.2 PSS0 CMO CPRL2 T2V.10 T2R.10 T2C.10 TCC2 T2V.2 T2R.2 T2C.2 CCF1 1 PO0.1 PO1.1 EX0 PI0.1 PI1.1 -- LBDE WTF WT5 PD0.1 PD1.1 KEN0.1 KEN1.1 SPE CPOL SS2 T2V.9 T2R.9 T2C.9 TF2L T2V.1 T2R.1 T2C.1 CCF0 0 PO0.0 PO1.0 IE0 PI0.0 PI1.0 HRNE BOD WTE WT4 PD0.0 PD1.0 KEN0.0 KEN1.0 TXC EXRF G2EN T2V.8 T2R.8 T2C.8 TC2L T2V.0 T2R.0 T2C.0 C/T2
MAXQ3210
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
Table 6. Peripheral Register Reset Values
REGISTER PO0 PO1 EI0 PI0 PI1 HRNC PWCN WUTC WUT PD0 PD1 KEN0 KEN1 ICDF CMPC T2CNA T2H T2RH T2CH T2CNB T2V T2R T2C T2CFG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGISTER BIT 15 14 13 12 11 10 9 8 7 1 0 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 1 1 0 s s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 1 1 0 s s 0 s 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 4 1 1 0 s s 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 1 0 s s 0 s 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 2 1 1 0 s s 0 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 1 1 1 0 s s 0 0 0 0 0 0 0 0 s 0 0 0 0 0 0 0 0 0 0 0 1 1 0 s s 0 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
System Timing
For maximum versatility, the MAXQ3210 generates its internal system clock from several sources: * External clock source, including low-cost operation from 3.58MHz "Colorburst" crystal * External crystal or ceramic resonator, using the internal oscillator * External RC, using the internal relaxation oscillator * Internal ring oscillator A crystal warmup counter enhances operational reliability. Each time the external crystal oscillation must restart, such as after exiting stop mode, the device initiates a crystal warmup period of 65,536 oscillations. This allows time for the crystal amplitude and frequency to stabilize before using it as a clock source. While in the warmup mode, the device operates from the internal 8kHz ring oscillator and can optionally switch back to the crystal as soon as the warmup period expires.
Internal Voltage Regulator
The MAXQ3210 features an internal voltage regulator that allows it to be powered from an external battery ranging from approximately 6.0V to 9.5V. A low-battery detect feature can set a flag and/or trigger an interrupt when enabled and the battery voltage falls below the VBF threshold. The battery voltage is regulated to an internal voltage (VDDINT) of approximately 5V. The REGOUT output pin provides 5V for use by external devices.
RESET RWT EWDI EWT
RESET
CLOCK
WATCHDOG TIMER
INTERNAL NANO-RING OSCILLATOR
MAXQ3210
XT/RC
GLITCH-FREE MUX
RC OSCILLATOR KILL
GLITCH-FREE MUX
CLOCK DIVIDER
SYSTEM CLOCK STOP
CRYSTAL/ RESONATOR OSCILLATOR KILL STOP RGSL XTE
RGMD XT/RC DIV 1 DIV 2 DIV 4 DIV 8 DIV 256
POR
CLOCK SELECTOR
STOP RGSL
RC CLK XT CLK RESET
X-DOG STARTUP TIMER
RGSL DONE
RGMD
Figure 2. Clock Sources
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
Power Management
Advanced power-management features minimize power consumption by dynamically matching the processing speed of the device to the required performance level. This means device operation can be slowed and power consumption minimized during periods of reduced activity. When more processing power is required, the microcontroller can increase its operating frequency. Software-selectable clock-divide operations allow flexibility, selecting whether a system clock cycle (SYSCLK) is 1, 2, 4, or 8 oscillator cycles. By performing this function in software, a lower power state can be entered without the cost of additional hardware. For extremely power-sensitive applications, additional low-power modes are available: * Divide-by-256 power-management mode (PMM) (PMME = 1, CD1:0 = 00b) * Stop mode (STOP = 1) In PMM, one system clock is 256 oscillator cycles, significantly reducing power consumption while the microcontroller functions at reduced speed. The optional switchback feature allows enabled interrupt sources including external interrupts to quickly exit the powermanagement modes and return to a faster internal clock rate. Power consumption reaches its minimum in stop mode. In this mode the external oscillator, system clock, and all processing activity is halted. Stop mode is exited when an enabled external interrupt pin is triggered, the enabled wake-up timer expires, or an external reset signal is applied to the RESET pin. Upon exiting stop mode, the microcontroller starts execution immediately from its internal 8kHz (approximately) ring oscillator while the warmup period completes. When an enabled interrupt is detected, software jumps to a user-programmable interrupt vector location. The IV register defaults to 0000h on reset or power-up, so if it is not changed to a different address, the user program must determine whether a jump to 0000h came from a reset or interrupt source. Once software control has been transferred to the ISR, the interrupt identification register (IIR) can be used to determine if a system register or peripheral register was the source of the interrupt. The specified module can then be interrogated for the specific interrupt source and software can take appropriate action. Because the interrupts are evaluated by user software, the user can define a unique interrupt priority scheme for each application. The following interrupt sources are available: * Watchdog Interrupt * External Interrupt 0 * Timer 2 Low Compare, Low Overflow, Capture/ Compare, and Overflow Interrupts * Analog Comparator Interrupt * Low-Battery Interrupt * Wake-Up Interrupt
Reset Sources
Several reset sources are provided for microcontroller control. Although code execution is halted in the reset state, the high-frequency oscillator and the ring oscillator continue to oscillate.
Power-On Reset/Brownout Reset
An internal power-on reset circuit enhances system reliability. This circuit forces the device to perform a power-on reset whenever a rising voltage on V DD climbs above approximately V RST. Additionally, the device performs a brownout reset whenever VDD drops below VRST, a feature that can be optionally disabled in stop mode. The following events occur during a poweron reset. * All registers and circuits enter their power-on reset state * I/O pins revert to their reset state, with logic-1 states tracking VREGOUT * The power-on reset flag is set to indicate the source of the reset * The ring oscillator becomes the clock source * The external high-speed oscillator begins its warmup * Code execution begins at location 8000h
Interrupts
Multiple reset sources are available for quick response to internal and external events. The MAXQ architecture uses a single interrupt vector (IV), single interrupt-service routine (ISR) design. For maximum flexibility, interrupts can be enabled globally, individually, or by module. When an interrupt condition occurs, its individual flag is set, even if the interrupt source is disabled at the local, module, or global level. Interrupt flags must be cleared within the user-interrupt routine to avoid repeated interrupts from the same source. Application software must ensure a delay between the write to the flag and the RETI instruction to allow time for the interrupt hardware to remove the internal interrupt condition. Asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a two-instruction delay.
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator
Watchdog Timer Reset
The watchdog timer functions are described in the MAXQ Family User's Guide. Software can determine if a reset is caused by a watchdog timeout by checking the Watchdog Timer Reset Flag (WTRF) in the WDCN register. Execution resumes at location 8000h following a watchdog timer reset.
I/O Ports
The microcontroller uses a form of Type D bidirectional I/O pins described in the MAXQ Family User's Guide. Each port has eight independent, general-purpose I/O pins and three configure/control registers. Many pins support alternate functions such as timers or interrupts, which are enabled, controlled, and monitored by dedicated peripheral registers. Using the alternate function automatically converts the pin to that function. The I/O pins on this device employ an optional "keeper" latch that helps to maintain the input pin state in the absence of external drive sources. Port 0.7 is a special pin with a stronger pulldown capability to drive devices such as LEDs. It operates and is configured the same as other pins. Type D port pins have Schmitt Trigger receivers and full CMOS output drivers, and can support special functions. The pin is either tri-stated or weak pullup when defined as an input, dependent on the state of the corresponding bit in the output register. One pin of the device has interrupt capability.
MAXQ3210
External System Reset
Asserting the external RESET pin low causes the device to enter the reset state. The external reset functions as described in the MAXQ Family User's Guide. Execution resumes at location 8000h after the RESET pin is released. The external system reset function is enabled by default on a power-on reset, but can be disabled and the pin used as general-purpose I/O by setting the Reset Pin Disable (RSTD) bit. The system designer is cautioned not to disable the reset pin early in the software as it could disable future JTAG access and/or bootloader capability.
VDD
WEAK
PD.x SF DIRECTION
MUX
VDDIO
SF ENABLE
PO.x SF OUTPUT
MUX
MAXQ3210
I/O PAD PIN.x
PI.x OR SF INPUT
FLAG
INTERRUPT FLAG
DETECT CIRCUIT
EIES.x
Figure 3. Type D Port Pin Schematic
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
Programmable Timer
The microcontroller incorporates one 16-bit programmable timer/counter. The type 2 timer (timer 2) can be used in counter/timer/capture/compare/PWM functions, allowing precise control of internal and external events. It also supports optional single-shot, external gating, and polarity control options. ed, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. This protects the system against electrical noise or electrostatic discharge (ESD) upsets that could cause uncontrolled processor operation. The internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability. The watchdog timer is controlled through bits in the WDCN register. Its timeout period can be set to one of four programmable intervals ranging from 2 12 to 221 system clocks in its default clock mode, allowing flexibility to support different types of applications. The interrupt occurs 512 system clocks before the reset, allowing the system to execute an interrupt and place the system in a known, safe state before the device performs a total system reset. At 3.58MHz, watchdog timeout periods can be programmed from 1.14ms to 149.94s, depending on the system clock mode.
Timer 2
The timer 2 peripheral includes the following: * 16-bit auto-reload timer/counter * 16-bit capture * 16-bit counter * 8-bit capture and 8-bit timer * 8-bit counter and 8-bit timer
Wakeup Timer
The microcontroller includes a simple 20-bit wake-up timer that can be used to measure long intervals. The user-selectable timer period can be used to generate a long-period interrupt or wake the device out of stop mode. The timer can be clocked from either the currently active system clock or the 8kHz ring oscillator. In stop mode only the 8kHz ring oscillator is available as the wakeup timer clock source. As an interrupt, the feature increases overall performance by reducing many shorter timer interruptions to a single interrupt to measure the same long period. When used in stop mode, it provides the energy savings of the lowest power mode with periodic wakeup ability.
Analog Comparator
The analog comparator is a one-bit, analog-to-digital comparator. The comparator input can be connected to a wide range of peripherals, including chemical sensors and motion or proximity detectors, or any other appropriate analog input. The comparator measures the analog input against either an external voltage reference or the internal +2.5V reference. When the level on the comparator input, CMPI, rises above the selected voltage reference, the CMO bit in the CMPC register is changed to the desired level. The device then responds by asserting an external signal and/or activating an internal interrupt request. The polarity of the external signal asserted is programmable. When not in use, the pins associated with the comparator are usable as general-purpose I/O. In addition, the +2.5V reference is configurable to be output on the VREF pin. This provides an absolute voltage reference for use with data converters or other precision devices.
Watchdog Timer
An internal watchdog timer greatly increases system reliability. The timer resets the device if software execution is disturbed. The watchdog timer is a free-running counter designed to be periodically reset by the application software. If software is operating correctly, the counter is periodically reset and never reaches its maximum count. However, if software operation is interrupt-
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
REF0 EXRF ENABLE REF0 STOP 0 1 GAIN = 1 VOUT +2.5V REFERENCE GENERATOR VIN +2.5V BANDGAP REFERENCE CMON STOP
EXRF CMON VREF (P0.4) 0 CMPI (P0.5) 1 CMON CMON STOP 0 1
(V+ > V-) CPOL 0 D > SYSTEM CLOCK Q 1 ECMO CMPO (P0.3)
CMF INTERRUPT REQUEST Q SET CMM ECMF
Figure 4. MAXQ3210 Analog Comparator
Piezoelectric Horn Driver
The piezoelectric horn driver provides circuitry to drive a 3-pin piezoelectric horn/annunciator. These horns contain a ceramic element that bends or expands when a voltage is applied, generating a single tone capable of reaching 100dB. They can be used in a wide variety of applications requiring audible alerts such as theft, intrusion proximity or fire alarms, chemical sensors, door sensors, and safety monitors.
The three-terminal piezoelectric horn is connected to the horn silver (HORNS), horn brass (HORNB), and feedback (FEED) pins, plus a dedicated ground for the horn driver (GNDHORN). The MAXQ3210 is designed to drive any industry-standard piezoelectric horn, allowing the designer maximum flexibility and lowest overall system cost. A single bit (HRNE) enables or disables the horn output, and software can toggle the bit to produce sounds of varying durations and patterns.
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
In-Circuit Debug
Embedded debugging capability is available through the JTAG-compatible Test Access Port. Embedded debug hardware and embedded ROM firmware provide in-circuit debugging capability to the user application, eliminating the need for an expensive in-circuit emulator. Figure 5 shows a block diagram of the in-circuit debugger. The in-circuit debug features include: * Hardware debug engine * Set of registers able to set breakpoints on register, code, or data accesses * Set of debug service routines stored in the utility ROM The embedded hardware debug engine is an independent hardware block in the microcontroller. The debug engine can monitor internal activities and interact with selected internal registers while the CPU is executing user code. Collectively, the hardware and software features allow two basic modes of in-circuit debugging: * Background mode allows the host to configure and set up the in-circuit debugger while the CPU continues to execute the application software at full speed. Debug mode can be invoked from background mode. * Debug mode allows the debug engine to take control of the CPU, providing read/write access to internal registers and memory, and single-step trace operation.
Applications Information
Grounds and Bypassing
Careful PC board layout significantly minimizes crosstalk among the reference input, comparator outputs, and digital inputs. Keep digital and analog lines separate, and use ground traces as shields between them where possible. Separate CMPI and VREF from each other by running a ground trace between these pins. Bypass VDD with a capacitor as low as 1F and keep bypass capacitor leads short for best noise rejection.
Capacitor Selection and Regulator Stability
For general purposes, use a combination of a 10F and 0.1F capacitor on REGOUT. Note that the 0.1F capacitor is always required on REGOUT and must be a good quality ceramic with low ESR. The internal regulator is designed to be stable with an output filter capacitor as low as 4.7F and an ESR as high as 6. Larger REGOUT capacitor values and lower ESR provide better supply-noise rejection and transient response. Note that some ceramic dielectric materials (e.g., Z5U and Y5V) exhibit a large temperature coefficient for both capacitance and ESR, and a larger REGOUT capacitance may be needed to ensure stability at low temperatures.
Applications
The low-power, high-performance RISC architecture of the MAXQ3210 makes it an excellent fit for many portable or battery-powered applications that require cost-effective computing. The analog comparator can function as an A/D converter when simple analog measurements are necessary, and the high-current I/O pin can drive a power or status LED. Combined with the high-output piezoelectric horn/transducer, the microcontroller can function as both the "brain" and "mouth" in a wide variety of monitoring applications. The microcontroller includes an on-chip voltage regulator that allows it to be powered directly off a 9V battery. A low-battery detector allows the microcontroller to monitor its own battery condition. The internal voltage regulator can also drive external 5V circuitry while a 9V battery drives the system. This device can also be used as a low-cost analog-todigital converter (ADC). The single-slope conversion method can be easily implemented using the internal comparator and an internal timer. The basic implementation of such a converter is illustrated below. One of the benefits of this approach is the small number of
MAXQ3210
DEBUG SERVICE ROUTINES (UTILITY ROM)
CPU DEBUG ENGINE TMS TCK TDI TDO TAP CONTROLLER CONTROL BREAKPOINT ADDRESS DATA
Figure 5. In-Circuit Debugger
22
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator
external components required: the transistor creates a constant current source, a ramp capacitor times the conversion, and a resistor and capacitor on the comparator input acting as a simple filter. The result is the addition of A/D capability to the end system at virtually no additional cost. including programming, available at www.maximic.com/MAXQUG. * The MAXQ Family User's Guide: MAXQ3210/ MAXQ3212 Supplement, which contains detailed information on features specific to the MAXQ3210, available at www.maxim-ic.com/MAXQ32xxSUP.
MAXQ3210
Additional Documentation
Designers must have four documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user's guides offer detailed information about device features and operation. The following documents can be downloaded from www.maxim-ic.com/microcontrollers: * The MAXQ3210 data sheet, which contains electrical/timing specifications and pin descriptions, available at www.maxim-ic.com/MAXQ3210. * The MAXQ3210 errata sheet for the specific device revision, available at www.maxim-ic.com/errata. * The MAXQ Family User's Guide, which contains detailed information on core features and operation,
Development and Technical Support
A variety of highly versatile, affordably priced development tools for this microcontroller are available from Maxim/Dallas Semiconductor and third-party suppliers, including: * Compilers * In-circuit emulators * Integrated development environments (IDEs) * JTAG-to-serial converters for programming and debugging A partial list of development tool vendors can be found at www.maxim-ic.com/MAXQ. Technical support is available through email at maxq.support@dalsemi.com.
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
Typical Chemical Sensor Application Using An External Voltage Reference
VDD 9V BATTERY
Px.x CHEMICAL SENSOR REGOUT 1k
SELF-TEST Px.x
MAXQ3210
P0.7/LED CMPI ANALOG SENSOR MAX6037 VOLTAGE REF OR EQUIVALENT (OPTIONAL)
22pF HFXIN 3.5795MHz
VREF HFXOUT 22pF GND HORNS GNDHORN 470k FEED 68k 2nF 30k HORNB
PIEZOELECTRIC ALARM
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator
Typical Chemical Sensor Application Using A Simple SAR ADC
MAXQ3210
REGOUT
Px.x
Px.x CHEMICAL SENSOR REGOUT 1k
VREF
MAXQ3210
INPUT P0.7/LED CMPI VDD 9V BATTERY 22pF HFXIN 3.5795MHz HFXOUT 22pF GND 470k GNDHORN FEED HORNB HORNS 68k 2nF 30k PIEZOELECTRIC ALARM
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
Ordering Information
PART MAXQ3210-EJX MAXQ3210-EJX+ MAXQ3210-EMX MAXQ3210-EMX+ TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C NOMINAL VDD (V) 9 9 9 9 MEMORY 1kWord EEPROM 1kWord EEPROM 1kWord EEPROM 1kWord EEPROM PIN-PACKAGE 24 TSSOP 24 TSSOP 24 PDIP 24 PDIP
+Denotes a Pb-free/RoHS-compliant package.
Pin Configuration
Rev 0; 1/06:
TOP VIEW
Revision History
Original release. Changed units on Active Current (Electrical Characteristics) from "A" to "mA" for IDD5 and IDD6. Rev 1; 5/06:
GND 1 VREF/P0.4 2 CMP0/P0.3 3 T2P/P0.2 4 T2PB/P0.1 5 P0.0 6 P1.6 7 P1.5 8 TDO/P1.4 9 TCK/P1.3 10 HFXIN 11 HFXOUT 12
24 CMPI/P0.5 23 INT/P0.6 22 LED/P0.7 21 TDI/P1.0
MAXQ3210
20 RESET/P1.1 19 TMS/P1.2 18 REGOUT 17 VDD 16 HORNS 15 GNDHORN 14 HORNB 13 FEED
PDIP/TSSOP
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
TSSOP4.40mm.EPS
MAXQ3210
PACKAGE OUTLINE, TSSOP 4.40mm BODY
21-0066
G
1 1
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Microcontroller with Internal Voltage Regulator, Piezoelectric Horn Driver, and Comparator MAXQ3210
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
is a registered trademark of Dallas Semiconductor Corporation.
Marichu Quijano
PDIPN.EPS

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